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hynix semiconductor 8-bit single-chip microcontrollers HMS81004E hms81008e hms81016e hms81024e hms81032e users manual (ver. 1.00)
version 1.00 published by sp mcu application team 2001 hynix semiconductor, inc. all right reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and repre- sentatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 table of contents 1. overview ...........................................1 description .........................................................1 features .............................................................1 development tools ............................................ 2 2. block diagram ..............................3 3. pin assignment (top view) ........... 4 4. package dimension .......................5 5. pin function .....................................8 6. port structures .........................10 7. electrical characteristics ...12 absolute maximum ratings .............................12 recommended operating conditions ..............12 dc electrical characteristics ............................12 remout port ioh characteristics graph ........13 remout port iol characteristics graph .........14 ac characteristics ...........................................14 8. memory organization ................16 registers ..........................................................16 program memory .............................................19 data memory ....................................................22 list for control registers.................................. 23 addressing mode .............................................25 9. i/o ports ..........................................30 r0 ports ........................................................... 30 r1 ports ...........................................................30 r2 port .............................................................32 10. clock generator ......................33 oscillation circuit .......................................... 34 11. basic interval timer ................36 12. watch dog timer .......................38 13. timer0, timer1, timer2 ....................39 14. interrupts ...................................47 interrupt priority and sources ........................ 48 interrupt control register ................................ 48 interrupt accept mode ................................... 49 interrupt sequence ........................................ 50 brk interrupt ................................................ 52 multi interrupt ................................................ 52 external interrupt ........................................... 52 key scan input processing ........................... 53 15.standby function ......................55 sleep mode .................................................... 55 stop mode .................................................. 55 standby mode release ......................... 56 release operation of standbymode58 16. reset function ..........................60 external reset ...................................... 60 power on reset ..................................... 60 low voltage detection mode ........................ 62 a. mask order sheet ........................ i b. instruction .................................... ii terminology list ...............................................ii instruction map ................................................. iii instruction set ..................................................iv
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 1 HMS81004E/08e/16e/24e/32e cmos single- chip 8-bit microcontroller for universal remote controller 1. overview 1.1 description the HMS81004E/08e/16e/24e/32e is an advanced cmos 8-bit microcontroller with 4/8/16/24/32k bytes of rom. the device is one of gms800 family. the hynix HMS81004E/08e/16e/24e/32e is a powerful microcontroller which provides a highly flexible and cost effective solution to many ur applications.the HMS81004E/08e/16e/24e/32e provides the fol- lowing standard features: 4/8/16/24/32k bytes of rom, 448 bytes of ram, 8-bit timer/counter, on-chip oscillator and clock circuitry. in addition, the HMS81004E/08e/16e/24e/32e supports power saving modes to reduce power consumption. 1.2 features ? instruction cycle time: - 1us at 4mhz ? programmable i/o pins ? operating voltage - 2.0 ~ 3.6 v @ 4mhz (mask) - 2.0 ~ 4.0 v @ 4mhz (otp) ?timer - timer / counter ......... 16bit * 1ch ......... 8bit * 2ch - basic interval timer ...... 8bit * 1ch - watch dog timer ............ 6bit * 1ch ? 8 interrupt sources - nested interrupt control is available. - external input: 2 - keyscan input - basic interval timer - watchdog timer - timer : 3 ? power on reset ? power saving operation modes - stop operation - sleep operation ? low voltage detection circuit ? watch dog timer auto start (during 1second after power on reset) device name rom size eprom size ram size package HMS81004E 4k bytes - 448 bytes ( included 256 bytes stack memory ) 20 sop/pdip 24 sop/skinny dip 28 sop/skinny dip hms81008e 8k bytes - hms81016e 16k bytes - hms81024e 24k bytes - hms81032e 32k bytes - hms81020tl - 20k bytes hms81032tl - 32k bytes 20 pin 24 pin 28 pin input 3 3 3 output 2 2 2 i/o 13 17 21
HMS81004E/08e/16e/24e/32e 2 june 2001 ver 1.00 1.3 development tools the HMS81004E/08e/16e/24e/32e are supported by a full-fea- tured macro assembler, an in-circuit emulator choice-dr. tm and otp programmers. macro assembler operates under the ms- windows 95/98 tm /nt4/w2000. please contact sales part of hynix software - ms- window base assembler - linker / editor / debugger hardware (emulator) - choice-dr. - choice-dr. eva 81c5eva otp program- mer - universal single programmer. - 4 gang programmer - stand alone
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 3 2. block diagram g8mc core ram (448byte) rom (32kbyte) prescaler & b.i.t watchdog timer timer interrupt key scan int. generation block clock gen. & system control r0 port r1 port r2 port remout r17/t0 r16/t1 r15/t2 r14/ec r12/int2 r11/int1 r00~r07 r10~r17 test reset xin xout r00~r07 r10~r17 r20~r24 vdd vss
HMS81004E/08e/16e/24e/32e 4 june 2001 ver 1.00 3. pin assignment (top view) r13 r12 r11 r10 vdd xout xin r00 r01 r02 r03 r20 r21 r22 r14 r15 r16 r17 remout reset test r07 r06 r05 r04 vss r24 r23 28pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 r13 r12 r11 r10 vdd xout xin r00 r01 r02 r03 r20 r14 r15 r16 r17 remout reset test r07 r06 r05 r04 vss 24pin 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 r11 r10 vdd xout xin r00 r01 r02 r03 r20 r16 r17 remout reset test r07 r06 r05 r04 vss 20pin 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 5 4. package dimension 1.043 0.021 0.065 0.100 bsc 0.300 bsc 0.270 0. 012 0 ~ 15 max 0.180 min 0.015 0.140 0.512 0.020 0.050 bsc 0 . 0 1 3 0 ~ 8 0.042 20 pdip 20 sop unit: inch max min 1.015 0.015 0.050 0.120 0.245 0. 0 08 0.229 0.291 0.419 0.398 0.495 0.093 0.105 0.013 0.012 0.004 0 . 0 0 8 0.016
HMS81004E/08e/16e/24e/32e 6 june 2001 ver 1.00 1.265 0.021 0.065 0.100 bsc 0.300 bsc 0.300 0. 0 14 0 ~ 15 max 0.180 min 0.015 0.140 0.614 0.020 0.050 bsc 0 . 0 1 3 0 ~ 8 0.042 24 skdip 24 sop unit: inch max min 1.160 0.015 0.045 0.120 0.250 0. 008 0.229 0.291 0.419 0.398 0.598 0.093 0.106 0.013 0.012 0.004 0 . 0 0 8 0.016
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 7 1.375 0.021 0.055 0.100 bsc 0.300 bsc 0.300 0. 0 14 0 ~ 15 max 0.180 min 0.015 0.140 0.713 0.020 0.050 bsc 0 . 0 1 3 0 ~ 8 0.042 28 skdip 28 sop unit: inch max min 1.355 0.015 0.045 0.120 0.275 0. 008 0.229 0.291 0.419 0.398 0.697 0.093 0.106 0.013 0.012 0.004 0 . 0 0 8 0.016
HMS81004E/08e/16e/24e/32e 8 june 2001 ver 1.00 5. pin function v dd : supply voltage. v ss : circuit ground. test : used for shipping inspection of the ic. for normal operation, it should be connected to v dd . reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. r00~r07 : r0 is an 8-bit cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r10~r17 : r1 is an 8-bit cmos bidirectional i/o port. r1 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r1 serves the functions of the various follow- ing special features . r20~r24 : r2 is an 8-bit cmos bidirectional i/o port. r2 pins 1 or 0 written to the port direction register can be used as outputs or inputs . port pin alternate function r11 r12 r14 r15 r16 r17 int1 (external interrupt input 1) int2 (external interrupt input 2) ec (event counter input ) t2 (timer / counter input 2) t1 (timer / counter input 1) t0 (timer / counter input 0)
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 9 pin name input/ output function @reset @stop r00 i/o - each bit of the port can be individually configured as an input or an output by user software - push-pull output - cmos input with pull-up resister (option) - can be programmable as key scan input - pull-up resisters are automatically disabled at output mode input state of before stop r01 i/o r02 i/o r03 i/o r04 i/o r05 i/o r06 i/o r07 i/o r10 i/o - each bit of the port can be individually configured as an input or an output by user software - push-pull output - cmos input with pull-up resister (option) - can be programmable as key scan input or open drain output - pull-up resisters are automatically disabled at output mode - direct driving of led(n-tr.) input state of before stop r11/int1 i/o r12/int2 i/o r13 i/o r14/ec i/o r15/t2 i/o r16/t1 i/o r17/t0 i/o r20 i/o - each bit of the port can be individually configured as an input or an output by user software - push-pull output - cmos input with pull-up resister (option) - pull-up resisters are automatically disabled at output mode - direct driving of led(n-tr.) input state of before stop r21 i/o r22 i/o r23 i/o r24 i/o xin i oscillator input low xout o oscillator output high remout o high current output l output l output reset i includes pull-up resistor l level state of before stop test i includes pull-up resistor vdd p positive power supply vss p groud
HMS81004E/08e/16e/24e/32e 10 june 2001 ver 1.00 6. port structures r0[0:7] r10, r13 r11/int1, r12/int2, r14/ec pin data reg. dir. reg. key scan pull up reg. rd v dd v ss pull-up tr. input open drain reg. data bus tr.: transistor reg.: register lvd circuit otp : connected mask : option (default connected) v dd ks_en standby release level control register mux mux pin data reg. function sele- key scan pull up reg. rd v dd v ss pull-up tr. input open drain reg. data bus tr.: transistor reg.: register lvd circuit otp : connected mask : option (default connected) v dd ks_en standby release level control register ction reg. dir reg. mux mux pin data reg. function sele- key scan pull up reg. rd v dd v ss pull-up tr. input open drain reg. data bus tr.: transistor reg.: register lvd circuit otp : connected mask : option (default connected) v dd ks_en standby release level control register ction reg. dir reg. mux noise filter to r11...int1 to r12...int2 to r14...ec mux
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 11 r15/t2, r16/t1, r17/t0 r2[0:4] test remout xin, xout reset pin data reg. function sele- key scan pull up reg. rd v dd v ss pull-up tr. input open drain reg. data bus tr.: transistor reg.: register lvd circuit otp : connected mask : option (default connected) v dd ks_en standby release level control register ction reg. dir reg. mux to r15...t2 to r16...t1 to r17...t0 mux mux pin data reg. dir. reg. pull up reg. rd v dd v ss pull-up tr. open drain reg. data bus tr.: transistor reg.: register lvd circuit otp : connected mask : option (default connected) v dd mux pin v dd v ss noise filter pin v dd v ss internal signal xin v ss xout noise filter from stop circuit pin v dd v ss noise filter from power on reset
HMS81004E/08e/16e/24e/32e 12 june 2001 ver 1.00 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ........................................... -0.3 to +5.0 v input voltage .....................................-0.3 to v dd +0.3 v output voltage ...................................-0.3 to v dd +0.3 v operating temperature........................................ 0~70 c storage temperature ...................................... -65~150 c power dissipation................................................700 ma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 7.2 recommended operating conditions 7.3 dc electrical characteristics (t a =-0~70 c, v dd =2.0~3.6v, gnd=0v) parameter symbol condition specifications unit min. max. supply voltage v dd f xin =4mhz 2.0 3.6 v operating frequency f xin v dd =2.0~3.6v 1.0 4.0 mhz operating temperature t opr -0+70 c parameter symbol condition specifications unit min. typ. max. high level input voltage v ih1 r11,r12,r14,reset 0.8 v dd - v dd v v ih2 r0,r1(except r11,r12,r14), r2 0.7 v dd - v dd v low level input voltage v il1 r11,r12,r14,reset 0- 0.2 v dd v v il2 r0,r1(except r11,r12,r14), r2 0 - 0.3 v dd v hign level input leakage current i ih r0,r1,r2,reset ,v ih = vdd --1 m a low level input leakage current i il r0,r1,r2,reset (without pull-up),v il = 0 ---1 m a high level output voltage v oh1 r0, i oh =-0.5ma vdd-0.4 - - v v oh2 r1[6:0], r2, i oh =-1.0ma vdd-0.4 - - v v oh3 xin, xout,i oh =-200 m a vdd-0.9 - - v low level output voltage v ol1 r0, i ol =1ma --0.4v v ol2 r1, r2, i ol =5ma --0.8v v ol3 xin, xout,i ol =200 m a --0.8v hign level output leakage current i ohl r0,r1,r2, v oh = vdd --1 m a low level output leakage current i oll r0,r1,r2, v ol = 0 ---1 m a
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 13 7.4 remout port ioh characteristics graph (typical process & room temperature) high level output current i oh remout, r17, v oh =2v -30 -12 -5 ma low level output cruuent i ol remout, v ol =1v 0.5 - 3 ma input pull-up current i p r0,r1,r2, reset , vdd=3v 15 30 60 m a power supply current i dd1 operating current ,fxin=4mhz, vdd=2.0v - 2.4 6 ma i dd2 operating current ,fxin=4mhz, vdd=3.6v - 4 10 ma i slp1 sleep mode current ,fxin=4mhz, vdd=2.0v -12ma i slp2 sleep mode current ,fxin=4mhz, vdd=3.6v -23ma i stp1 stop mode current ,oscillator stop vdd=2.0v -28 m a i stp2 stop mode current ,oscillator stop vdd=3.6v -310 m a ram retention supply voltage v ret -0.7--v parameter symbol condition specifications unit min. typ. max. . figure 7-1 ioh vs voh 0 ioh(ma) voh ( v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -5 -10 -15 -20 -25 -30 vdd 2v vdd 3v vdd 4v
HMS81004E/08e/16e/24e/32e 14 june 2001 ver 1.00 7.5 remout port iol characteristics graph (typical process & room temperature) 7.6 ac characteristics (t a =0~+70 c, v dd =2.0~3.6v , v ss =0v) . figure 7-2 iol vs vol 5 iol(ma) vol ( v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4 3 2 1 0 -1 vdd 3v vdd 4v vdd 2v parameter symbol pins specifications unit min. typ. max. external clock input cycle time t cp x in 250 500 1000 ns system clock cycle time t sys 500 1000 2000 ns external clock pulse width high t cph x in 40 - - ns external clock pulse width low t cpl x in 40 - - ns external clock rising time t rcp x in - - 40 ns external clock falling time t fcp x in - - 40 ns interrupt pulse width high t ih int1, int2 2 - - t sys interrupt pulse width low t il int1, int2 2 - - t sys reset input pulse width low t rstl reset 8- - t sys event counter input pulse width high t ech ec 2- - t sys event counter input pulse width low t ecl ec 2- - t sys event counter input pulse rising time t rec ec --40 ns event counter input pulse falling time t fec ec --40 ns
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 15 figure 7-3 timing diagram t rcp t fcp x in int1 int2 0.5v v dd -0.5v 0.2v dd 0.8v dd 0.2v dd reset 0.2v dd 0.8v dd ec t il t ih t rstl t ecl t ech t cp t cph t cpl
HMS81004E/08e/16e/24e/32e 16 june 2001 ver 1.00 8. memory organization the HMS81004E/08e/16e/24e/32e has separate address spaces for program memory and data memory. program memory can only be read, not written to. it can be up to 32k bytes of program memory. data memory can be read and written to up to 448 bytes including the stack area. 8.1 registers this device has six registers that are the program counter (pc), an accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. in the case of multiplication instruction, execute as a mul- tiplier register. after multiplication operation, the lower 8- bit of the result enters. (y*a => ya). in the case of divi- sion instruction, execute as the lower 8-bit of dividend. af- ter division operation, quotient enters. figure 8-2 configuration of ya 16-bit register x, y registers: in the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. these modes are ex- tremely effective for referencing subroutine tables and memory tables. the index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. ? x register in the case of division instruction, execute as register. ? y register in the case of 16-bit operation instruction, execute as the upper 8-bit of ya. (16-bit accumulator). in the case of multiplication instruction, execute as a multiplicand regis- ter. after multiplication operation, the upper 8-bit of the result enters. in the case of division instruction, execute as the upper 8-bit of dividend. after division operation, re- mains enters. y register can be used as loop counter of conditional branch command. (e.g.dbne y, rel) stack pointer: the stack pointer is an 8-bit register used for occurrence interrupts, calling out subroutines and push, pop, reti, ret instruction. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the sp is post-decremented when a subrou- tine call or a push instruction is executed, or when an inter- rupt is accepted. the sp is pre-incremented when a return or a pop instruction is executed. the stack can be located at any position within 100 h to 1ff h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the loca- tion with which the use of the stack starts) by using the ini- tialization routine. normally, the initial value of "ff h " is a accumulator x register y register stack pointer program counter program status word x y sp pcl pch psw two 8-bit registers can be used as a "ya" 16-bit register y a y a
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 17 used. figure 8-3 stack operation program counter: the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset routine address (pc h :0ff h , pc l :0fe h ). program status word: the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 8-4 . it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. sp 01 h stack address ( 100 h ~ 1ff h ) 15 0 87 hardware fixed caution: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0ffh txsp ; sp ? ff h at execution of a call/tcall/pcall pcl pch 01ff sp after execution sp before execution 01fd 01fe 01fd 01fc 01ff push down at acceptance of interrupt pcl pch 01ff 01fc 01fe 01fd 01fc 01ff push down psw at execution of ret instruction pcl pch 01ff 01ff 01fe 01fd 01fc 01fd pop up at execution of reti instruction pcl pch 01ff 01ff 01fe 01fd 01fc 01fc pop up psw 0100h 01ffh stack depth at execution of push instruction a 01ff 01fe 01fe 01fd 01fc 01ff push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01ff 01ff 01fe 01fd 01fc 01fe pop up pop a (x,y,psw)
HMS81004E/08e/16e/24e/32e 18 june 2001 ver 1.00 [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. figure 8-4 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to "0". this flag immedi- ately becomes "0" when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is 1 page. it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value : 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands select direct page when g=1, page is addressed by rpr
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 19 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 4/8/16/24/32k bytes pro- gram memory space only physically implemented. ac- cessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5 , shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 8-6 . as shown in figure 8-5 , each area is assigned a fixed lo- cation in program memory. program memory area con- tains the user program. figure 8-5 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7 . example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to loca- tion 0fffa h . the interrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for external interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general purpose program memory. figure 8-6 interrupt vector area tcall area interrupt vector area ff00 h ffc0 h ffe0 h ffff h pcall area a000 h 8000 h f000 h e000 h c000 h HMS81004E 4krom hms81008e 8krom hms81016e 16 krom hms81024e 24krom hms81032e 32krom lda #5 tcall 0fh ; 1byte instruction :; instead of 2 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 e0 e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe - - - basic interval timer interrupt vector area - - timer2 interrupt vector area timer0 interrupt vector area - external interrupt 2 vector area key scan interrupt vector area reset vector area external interrupt 1 vector area timer1 interrupt vector area watch dog timer interrupt vector area "-" means reserved area. note: - 0ffde h s/w interrupt vector area
HMS81004E/08e/16e/24e/32e 20 june 2001 ver 1.00 figure 8-7 pcall and tcall memory area pcall ? ? ? ? rel 4f35 pcall 35h tcall ? ? ? ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffbf h pcall area (192 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35h 0ff00h 0ffffh 11111111 11010110 01001010 pc: f h f h d h 6 h 4a ~ ~ ~ ~ 25 0ffd6h 0ff00h 0ffffh d1 next 0ffd7h ? 0d125h reverse
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 21 example: the usage software example of vector address and the initialize part. org 0ffe0h dw not_used dw not_used dw not_used dw bit_int ; bit dw wdt_int ; watch dog timer dw not_used dw not_used dw tmr2_int ; timer-2 dw tmr1_int ; timer-1 dw tmr0_int ; timer-0 dw not_used ; dw int2 ; int.2 dw int1 ; int.1 dw key_int ; key scan dw not_used ; dw reset ; reset org 08000h ;hms81032e program start address ;******************************************** ; main program * ;******************************************** ; reset: nop clrg di ;disable all interrupts ldx #0 ram_clr: lda #0 ;ram clear(!0000h->!00bfh) sta {x}+ cmpx #0c0h bne ram_clr ; ldx #0ffh ;stack pointer initialize txsp ldm r0, #0 ;normal port 0 ldm r0dd,#1000_0010b ;normal port direction ldm p0pc,#1000_0010b ;pull up selection set ldm pmr1,#0000_0010b ;r1 port / int : : ldm ckctlr,#0011_1101b ;wdt on , 16ms time delay after stop mode release : :
HMS81004E/08e/16e/24e/32e 22 june 2001 ver 1.00 8.3 data memory figure 8-8 shows the internal data memory space availa- ble. data memory is divided into 3 groups, a user ram, control registers, stack. figure 8-8 data memory map user memory the HMS81004E/08e/16e/24e/32e has 448 8 bits for the user memory (ram). control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction. example; to write at ckctlr ldm clctlr,#09h ;divide ratio ?16 stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 8-3 on page 17. ram (192 bytes) control registers 0000h 00bfh 00c0h 00ffh 0100h 01ffh page0 page1 ram (stack) (256 bytes)
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 23 8.4 list for control registers address function register symbol read write reset value 00c0h port r0 data reg. r0 r/w undefined 00c1h port r0 data direction reg. r0dd w 00000000b 00c2h port r1 data reg. r1 r/w undefined 00c3h port r1 data direction reg. r1dd w 00000000b 00c4h port r2 data reg. r2 r/w undefined 00c5h port r2 data direction reg. r2dd w 00000000b 00c6h reserved 00c7h clock control reg. ckctlr w --110111b basic interval reg. btr r undefined 00c8h watch dog timer reg. wdtr w -0001111b 00c9h port r1 mode reg. pmr1 w 00000000b 00cah int. mode reg. imod r/w -0000000b 00cbh ext. int. edge selection ieds w 00000000b 00cch int. enable reg. low ienl r/w -00-----b 00cdh int. request flag reg. low irql r/w -00-----b 00ceh int. enable reg. high ienh r/w 000-000-b 00cfh int. request flag reg. high irqh r/w 000-000-b 00d0h timer0 (16bit) mode reg. tm0 r/w 00000000b 00d1h timer1 (8bit) mode reg. tm1 r/w 00000000b 00d2h timer2 (8bit) mode reg. tm2 r/w 00000000b 00d3h timer0 high-msb data reg. t0hmd w undefined 00d4h timer0 high-lsb data reg. t0hld w undefined 00d5h timer0 low-msb data reg. t0lmd w undefined timer0 high-msb count reg. r undefined 00d6h timer0 low-lsb data reg. t0lld w undefined timer0 low-lsb count reg. w undefined 00d7h timer1 high data reg. t1hd w undefined 00d8h timer1 low data reg. t1ld w undefined timer1 low count reg. r undefined 00d9h timer2 data reg. t2dr w undefined timer2 count reg. r undefined 00dah timer0 / timer1 mode reg. tm01 r/w 00000000b 00dbh reserved 00dch standby mode release reg0 smpr0 r/w 00000000b 00ddh standby mode release reg0 smpr1 r/w 00000000b 00deh port r1 open drain assign reg. r1odc r/w 00000000b
HMS81004E/08e/16e/24e/32e 24 june 2001 ver 1.00 00dfh port r2 open drain assign reg. r2odc r/w 00000000b 00e0h reserved 00e1h reserved 00e2h reserved 00e3h reserved 00e4h port r0 open drain assign reg. r0odc r/w 00000000b 00e5h reserved 00e6h reserved 00e7h reserved 00e8h reserved 00e9h reserved 00eah reserved 00ebh reserved 00ech reserved 00edh reserved 00eeh reserved 00efh reserved 00f0h sleep mode reg. slpm w - - - - - - - 0b 00f1h reserved 00f2 reserved 00f3h reserved 00f4h reserved 00f5h reserved 00f6h standby release level cont. reg. 0 srlc0 w 00000000b 00f7h standby release level cont. reg. 1 srlc1 w 00000000b 00f8h port r0 pull-up reg. cont. reg. r0pc w 00000000b 00f9h port r1 pull-up reg. cont. reg. r1pc w 00000000b 00fah port r2 pull-up reg. cont. reg. r2pc w 00000000b 00fbh reserved 00fch reserved 00fdh reserved 00feh reserved 00ffh reserved registers are controlled by byte manipulation instruction such as ldm etc., do not use bit manipulation w registers are controlled by both bit and byte manipulation instruction. r/w instruction such as set1, clr1 etc. if bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. - : this bit location is reserved.
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 25 8.5 addressing mode the HMS81004E/08e/16e/24e/32e uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: 0435 adc #35h when g-flag is 1, then ram address is difined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1, rpr=0ch e45535 ldm 35h,#55h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; g=0 c535 lda 35h ;a ? ram[35h] (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data , i.e. second byte(operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 35 a+35h+c ? a 04 memory e4 0f100 h data ? 55h ~ ~ ~ ~ data 0c35 h 35 0f102 h 55 0f101 h ? data 35 35 h 0e551 h data ? a ? ~ ~ ~ ~ c5 0e550 h
HMS81004E/08e/16e/24e/32e 26 june 2001 ver 1.00 0735f0 adc !0f035h ;a ? rom[0f035h] 07 0f100 h ~ ~ ~ ~ data 0f035 h f0 0f102 h 35 0f101 h ? a+data+c ? a address: 0f035
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 27 the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regard- less of g-flag and rpr. 983501 inc !0135h ;a ? rom[135h] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1, rpr=01 h d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h c645 lda 45h+x 98 0f100 h ~ ~ ~ ~ data 135 h 01 0f102 h 35 0f101 h ? data+1 ? data address: 0135 data d4 115 h 0e550 h data ? a ? ~ ~ ~ ~ data db 35 h data ? a ? ~ ~ ~ ~ 36h ? x data 45 3a h 0e551 h data ? a ? ~ ~ ~ ~ c6 0e550 h 45h+0f5h=13ah
HMS81004E/08e/16e/24e/32e 28 june 2001 ver 1.00 y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory. this addressing mode can specify mem- ory in whole area. example; y=55 h d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data(or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 3f35 jmp [35h] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h 1625 adc [25h+x] d5 0f100 h data ? a ~ ~ ~ ~ data 0fa55 h 0fa00h+55h=0fa55h fa 0f102 h 00 0f101 h ? 0a 35 h jump to address 0e30a h ~ ~ ~ ~ 35 0fa00 h e3 36 h ? 3f 0e30a h next ~ ~ ~ ~ 05 35 h 0e005 h ~ ~ ~ ~ 25 0fa00 h e0 36 h 16 0e005 h data ~ ~ ~ ~ a + data + c ? a 25 + x(10) = 35 h ?
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 29 y indexed indirect ? ? ? ? [dp]+y processes momory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h 1725 adc [25h]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; g=0 1f25e0 jmp [!0c025h] 05 25 h 0e005 h + y(10) = 0e015 h ~ ~ ~ ~ 25 0fa00 h e0 26 h ? 17 0e015 h data ~ ~ ~ ~ a + data + c ? a 25 0e025 h jump to ~ ~ ~ ~ e0 0fa00 h e7 0e026 h ? 25 0e725 h next ~ ~ ~ ~ 1f program memory address 0e30a h
HMS81004E/08e/16e/24e/32e 30 june 2001 ver 1.00 9. i/o ports the HMS81004E/08e/16e/24e/32e has 24 i/o ports which are port0(8 i/o), port1 (8 i/o), port2 (8 i/o). pull-up resistor of each port can be selectable by program. each port contains data direction register which controls i/ o and data register which stores port data. 9.1 r0 ports r0 is an 8-bit cmos bidirectional i/o port (address 0c0 h ). each i/o pin can independently used as an input or an output through the r0dd register (address 0c1 h ). r0 has internal pull-ups that is independently connected or disconnected by r0pc. the control registers for r0 are shown below. (1) r0 i/o data direction register (r0dd) r0 i/o data direction register (r0dd) is 8-bit register, and can assign input state or output state to each bit. if r0dd is 1, port r0 is in the output state, and if 0, it is in the input state. r0dd is write-only register. since r0dd is initialized as 00h in reset state, the whole port r0 becomes input state. (2) r0 data register (r0) r0 data register (r0) is 8-bit register to store data of port r0. when set as the output state by r0dd, and data is writ- ten in r0, data is outputted into r0 pin. when set as the in- put state, input state of pin is read. the initial value of r0 is unknown in reset state. (3) r0 open drain assign register (r0odc) r0 open drain assign register (r0odc) is 8bit register, and can assign r0 port as open drain output port each bit, if corresponding port is selected as output. if r0odc is selected as 1, port r0 is open drain output, and if select- ed as, 0 it is push-pull output. r0odc is write-only reg- ister and initialized as 00h in reset state. (4) r0 pull-up control register (r0pc) r0 pull-up control register (r0pc) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. if r0pc is selected as 1, pull-up ia disabled and if selected as 0, it is enabled. r0pc is write- only register and initialized as 00h in reset state. the pull-up is automatically disabled, if corresponding port is selected as output. 9.2 r1 ports r1 is an 8-bit cmos bidirectional i/o port (address 0c2 h ). each i/o pin can independently used as an input or an output through the r1dd register (address 0c3 h ). r1 has internal pull-ups that is independently connected or disconnected by register r1pc. the control registers for r1 are shown below. r0 data register (r/w) r0 address : 0c0 h reset value : undefined r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register (w) r0dd address : 0c1 h reset value : 00 h 0: input 1: output pull-up select r0 pull-up control register (w) r0pc address :0f8 h reset value : 00 h 1: without pull-up 0: with pull-up open drain select r0 open drain assign register (w) r0odc address :0e4 h reset value : 00 h 0: push-pull 1: open drain
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 31 (1) r1 i/o data direction register (r1dd) r1 i/o data direction register (r1dd) is 8-bit register, and can assign input state or output state to each bit. if r1dd is 1, port r1 is in the output state, and if 0, it is in the input state. r1dd is write-only register. since r1dd is initialized as 00h in reset state, the whole port r1 becomes input state. (2) r1 data register (r1) r1 data register (r1) is 8-bit register to store data of port r1. when set as the output state by r1dd, and data is written in r1, data is outputted into r1 pin. when set as the input state, input state of pin is read. the initial value of r1 is unknown in reset state. (3) r1 open drain assign register (r1odc) r1 open drain assign register (r1odc) is 8bit register, and can assign r1 port as open drain output port each bit, if corresponding port is selected as output. if r1odc is selected as 1, port r1 is open drain output, and if select- ed as 0, it is push-pull output. r1odc is write-only reg- ister and initialized as 00h in reset state. (4) r1 port mode register (pmr1) r1 port mode register (pmr1) is 8-bit register, and can assign the selection mode for each bit. when set as 0, corresponding bit of pmr1 acts as port r1 selection mode, and when set as 1, it becomes function selection mode. pmr1 is write-only register and initialized as 00h in re- set state. therefore, becomes port selection mode. port r1 can be i/o port by manipulating each r1dd bit, if cor- responding pmr1 bit is selected as 0. (5) r1 pull-up control register (r1pc) r1 pull-up control register (r1pc) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. if r1pc is selected as 1, pull-up ia disabled and if selected as 0, it is enabled. r1pc is write- only register and initialized as 00h in reset state. the r1 data register (r/w) r1 address : 0c2 h reset value : undefined r17 r16 r15 r14 r13 r12 r11 r10 port direction r1 direction register (w) r1dd address : 0c3 h reset value : 00 h 0: input 1: output pull-up select r1 pull-up control register (w) r1pc address : 0f9 h reset value : 00 h 1: without pull-up 0: with pull-up open drain select r1 open drain assign register (w) p1odc address : 0de h reset value : 00 h 0: push-pull 1: open drain mode select r1 port mode register (w) pmr1 address : 0c9 h reset value : 00 h 0: port r1 selection 1: function selection pin name pmr1 selection mode remarks t0s 0 r17 (i/o) - 1 t0 (o) timer0 t1s 0 r16 (i/o) - 1 t1 (o) timer1 t2s 0 r15 (i/o) - 1 t2 (o) timer2 ecs 0 r14 (i/o) - 1ec (i) timer0 event int2s 0 r12 (i/o) 1 int2 (i) timer0 input cap- ture int1s 0 r11 (i/o) 1 int1 (i) table 9-1 selection mode of pmr1
HMS81004E/08e/16e/24e/32e 32 june 2001 ver 1.00 pull-up is automatically disabled, if corresponding port is selected as output. 9.3 r2 port r2 is an 8-bit cmos bidirectional i/o port (address 0c4 h ). each i/o pin can independently used as an input or an output through the r2dd register (address 0c5 h ). r2 has internal pujll-ups that is independently connected or disconnected by r2pc (address 0fa h ). the control reg- isters for r2 are shown as below. (1) r2 i/o data direction register (r2dd) r2 i/o data direction register (r2dd) is 8-bit register, and can assign input state or output state to each bit. if r2dd is 1, port r2 is in the output state, and if 0, it is in the input state. r2dd is write-only register. since r2dd is initialized as 00h in reset state, the whole port r2 becomes input state. (2) r2 data register (r2) r2 data register (r2) is 8-bit register to store data of port r2. when set as the output state by r2dd, and data is writ- ten in r2, data is outputted into r2 pin. when set as the in- put state, input state of pin is read. the initial value of r2 is unknown in reset state. (3) r2 open drain assign register (r2odc) r2 open drain assign register (r2odc) is 8bit register, and can assign r2 port as open drain output port each bit, if corresponding port is selected as output. if r2odc is selected as 1, port r2 is open drain output, and if select- ed as 0, it is push-pull output. r2odc is write-only reg- ister and initialized as 00h in reset state. (4) r2 pull-up control register (r2pc) r2 pull-up control register (r2pc) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. if r2pc is selected as 1, pull-up ia disabled and if selected as 0, it is enabled. r2pc is write- only register and initialized as 00h in reset state. the pull-up is automatically disabled, if corresponding port is selected as output. r2 data register (r/w) r2 address : 0c4 h reset value : undefined -- r24 r23 r22 r21 r20 port direction r2 direction register (w) r2dd address : 0c5 h reset value : 00 h 0: input 1: output pull-up select r2 pull-up control register (w) r2pc address :0fa h reset value : 00 h 1: without pull-up 0: with pull-up open drain select r2 open drain assign register (w) r2odc address :0df h reset value : 00 h 0: push-pull 1: open drain -
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 33 10. clock generator clock generating circuit consists of clock pulse generator (c.p.g), prescaler, basic interval timer (b.i.t) and watch dog timer. the clock applied to the xin pin divided by two is used as the internal system clock. prescaler consist of 12-bit binary counter. the clock sup- plied from oscillation circuit is input to prescaler(fex) the divided output from each bit of prescaler is provided to periphera hardwarel clock to peripheral hardware can be stopped by bit4 (en- pck) of ckctlr register. enpck is set to 1 in reset state. clock control register (w) ckctlr address : 0c7 h initial value : --110111b 0 1 2 3 4 5 6 7 enpck 0: stopped 1: provided figure 10-1 block diagram of clock generator internal system clock (cpu clock) prescaler ? 1 peripheral clock ? 2 ? 4 ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 clock pulse f ex (mhz) ps0 ps3 ps2 ps4 ps1 ps10 ps9 ps5 ps6 ps7 4 frequency period 4m 1m 500k 250k 2m 125k 62.5k 250n 500n 1u 2u 4u 8u 16u 32u 64u 256u 128u 3.906k 7.183k 15.63k 31.25k ps8 generator osc circuit ps11 ps12 1.953k 512u 0.976k 1024u ps11 ps12 ? 2048 ? 4096 fex
HMS81004E/08e/16e/24e/32e 34 june 2001 ver 1.00 10.1 oscillation circuit oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. figure 10-2 shows circuit diagrams using a crystal (or ceramic) oscillator. as shown in the diagram, oscillation circuits can be construct- ed by connecting a oscillator between xout and xin. colck from oscillation circuit makescpu clock via clock pulse generator, and then enters prescaler to make peripheral hardware clock. alternately, the oscillator may be driven from an esternal source as figure 10-3 . in the stop mode,oscillation stop, xout state goes to high , xin state goes to low , and built-in feed back resistor is dis- abled. oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. in addition, see figure 10- 4 for the layout of the crystal. note: minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wir- ing to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high cur- rent is present. do not fetch signals from the oscillator. figure 10-4 recommend layout of oscillator pcb circuit figure 10-2 external crystal(ceramic) oscillator circuit figure 10-3 external clock input circuit xout xin vss cout cin xout xin vss open external clock source x out x in
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 35 frequency resonator maker part name load capacitor operating voltage 2.00mhz cq ztt2.00 cin=cout=open 2.0~3.6 cq zta2.00 cin=cout=30pf 2.0~3.6 murata cstls2m00g56-b0 cin=cout=open 2.0~3.6 murata cstcc2.00mg0h6 cin=cout=open 2.0~3.6 murata cstcc2m00g56-r0 cin=cout=open 2.0~3.6 4.00mhz cq ztt4.00 cin=cout=open 2.0~3.6 cq zta4.00 cin=cout=30pf 2.0~3.6 murata csts0400mg06 cin=cout=open 2.0~3.6 murata cstls4m00g56-b0 cin=cout=open 2.0~3.6 murata cstcr4m00g55-r0 cin=cout=open 2.0~3.6 tdk fcr4.0mc5 cin=cout=open 2.0~3.6 tdk fcr4.0msc5 cin=cout=open 2.0~3.6 coreteck crt4.00ms cin=cout=open 2.0~3.6 coreteck crm4.00ms cin=cout=30pf 2.0~3.6 table 10-1 recommendalbe resonator
HMS81004E/08e/16e/24e/32e 36 june 2001 ver 1.00 11. basic interval timer the HMS81004E/08e/16e/24e/32e has one 8-bit basic interval timer that is free-run and can not stop. block dia- gram is shown in figure 11-1 . the basic interval timer generates the time base for standby release time, watchdog timer counting, and etc. it also provides a basic interval timer interrupt (ifbit). as the count overflow from ff h to 00 h , this overflow causes the interrupt to be generated. -8bit binary up-counter -use the bit output of prescaler as input to secure the oscil- lation stabilization time after power-on -secures the oscillation stabilization time in standby mode (stop mode) release -contents of b.i.t can be read -provides the clock for watch dog timer the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 11-2 . if bit3(btcl) of ckctlr is set to 1, b.i.t is cleared, and then, after one machine cycle, btcl becomes 0, and b.i.t starts counting. btcl is set to ``0`` in reset state. the input clock of b.i.t can be selected from the prescaler within a range of 2us to 256us by clock input selection bits (bts2~bts0). (at fex = 4mhz). in reset state, or power on reset, bts2=1, bts1= 1, bts0= 1 to secure the longest oscillation stabilization time. b.i.t can generate the wide range of basic interval time interrupt request (if- bit) by selecting prescaler output. by reading of the basic interval timer register (bitr), we can read counter value of b.i.t. because b.i.t can be cleared or read, the spending time up to maximum 65.5ms can be available. b.i.t is read-only register. if b.i.t reg- ister is written, then ckctlr register with same address is written. figure 11-1 block diagram of basic interval timer mux basic interval timer interrupt select input clock 3 basic interval timer source clock 8-bit up-counter bts[2:0] btcl ? 8 ? 1024 ? 512 ? 256 ? 128 ? 64 ? 32 ? 16 to watchdog timer (wdtr) ckctlr clear overflow internal bus line clock control register [0c7 h ] ifbit read prescaler bitr
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 37 figure 11-2 ckctlr and bitr bts[2:0] cpu source clock b.i.t. input clock@4mhz(us) standby release time(ms) 000 001 010 011 100 101 110 111 ? 8 ? 16 ? 32 ? 64 ? 128 ? 256 ? 512 ? 1024 2 4 8 16 32 64 128 256 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536 btcl 76543210 - - bts1 basic interval timer source clock select 000: f xin ? 8 001: f xin ? 16 010: f xin ? 32 011: f xin ? 64 100: f xin ? 128 101: f xin ? 256 110: f xin ? 512 111: f xin ? 1024 clear bit 0: normal operation, free-run 1: clear 8-bit counter (bitr) to 0 and count up again. initail value: --110111 b address: 0c7 h ckctlr initial value: undefined address: 0c7 h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution: 8-bit free-run binary counter bts0 bts2 btcl btcl 76543210 r ww ww w rr r rr r r enpck this bit becomes to 0 automatically after one machine cycle. periphral clock 0:stopped 1:provided wdton w watch dog timer function control 0:6bit timer 1:watch dog timer
HMS81004E/08e/16e/24e/32e 38 june 2001 ver 1.00 12. watch dog timer watch dog timer (wdt) consists of 6-bit binary counter, 6-bit comparator, and watch dog timer register (wdtr).watch dog timer can be used 6-bit general tim- er or specific watch dog timer by setting bit5 (wdton) of clock control register (ckctlr).by assigning bit6(wdtcl) of wdtr, 6-bit counter can be cleared. wdt interrupt (ifwdt) interval is determined by the in- terrupt ifbit interval of basic interval timer and the val- ue of wdt register. -interval of ifwdt = (ifbit interval) * (wdtr value) as ifbit (basic interval timer interrupt request) is used for input clock of wdt, input clock cycle is possible from 512 us to 65,536 us by bts. (at fex = 4mhz) *at hardware reset time,wdt starts automatically. therefore the user must select the ckctlr and wdtr before wdt overflow. -reset wdtr value = 0f h ,=15 -interval of wdt = 65,536 * 15 = 983040 us (about 1second ) note: when wdtr register value is 63 (3fh) (caution) : do not use 0 for wdtr register value. device come into the reset state by wdt figure 12-1 block diagram of watch dog timer ifwdt wdt interrupt wdtr (6-bit) wdt (6-bit) comparator wdt btcl 76543210 - initial value: -0001111 b address: 0c8 h wdtr wdtcl [0c8 h ] wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 watch dog timer operation 0:free-run 1:automatically cleared, after one machine cycle ifbit wdton to reset circuit clear 6
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 39 13. timer0, timer1, timer2 (1) timer operation mode timer consists of 16bit binary counter timer0 (t0), 8bit binary timer1 (t1), timer2 (t2), timer data register, timer mode register (tm01, tm0, tm1, tm2) and con- trol circuit. timer data register consists of timer0 high- msb data register (t0hmd), timer0 high-lsb data register (t0hld), timer0 low-msb data register (t0lmd), timer0 low-lsb data register (t0lld), timer1 high data register (t1hd), timer1 low data register (t1ld), timer2 data register (t2dr). any of the ps0 ~ ps5, ps11 and external event input ec can be selected as clock source for t0. any of the ps0 ~ ps3, ps7 ~ ps10 can be selected as clock t1. any of the ps5 ~ ps12 can be selected as clock source for t2. * relevant port mode register (pmr1 : 00c9h) value should be assigned for event counter. timer0 - 16-bit interval timer - 16-bit event counter - 16-bit input capture - 16-bit rectangular-wave output - single/modulo-n mode - timer output initial value setting - timer0~timer1 combination logic output - one interrupt generating every 2nd counter overflow timer1 - 8-bit interval timer - 8-bit rectangular-wave output timer2 - 8-bit interval timer - 8-bit rectangular-wave output - modulo-n mode table 13-1 timer operation 16bit timer (t0) 8bit timer (t1) 8bit timer (t2) resolution max. count resolution max. count resolution max. count ps0 (0.25us) 16,384us ps0 (0.25us) 64us ps5 (8us) 2,048us ps1 (0.5us) 32,768us ps1 (0.5us) 128us ps6 (16us) 4,096us ps2 (1us) 65,536us ps2 (1us) 256us ps7 (32us) 8,192us ps3 (2us) 131,072us ps3 (2us) 512us ps8 (64us) 16,384us ps4 (4us) 262,144us ps7 (32us) 8,192us ps9 (128us) 32,768us ps5 (8us) 524,288us ps8 (64us) 16,384us ps10 (256us) 65,536us ps11 (512us) 33,554,432us ps9 (128us) 32,768us ps11 (512us) 131,072us ec - ps10 (256us) 65,536us ps12 (1024us) 262,144us table 13-2 function of timer & counter
HMS81004E/08e/16e/24e/32e 40 june 2001 ver 1.00 figure 13-1 block diagram of timer/counter t0hmd t0lmd t0lmd t0lld t1hd t1ld t2dr timer0 (16bit) polarity timer2(8bit) timer1(8bit) selection edge selection tout logic btcl -tout1 tout0 t0outp touts toutb t0init t1init 70 tm01 from ec /r14 from int2/r12 (capture signal) t0out (r17) tout (remout) t1out (r16) t2out (r15) btcl 76543210 - initial value: 00 h address: 0da h tm01 tout1 tout0 r/w r/w r/w r/w r/w t0outp timer 01 mode register tout logic 0: timer1 output low 1: timer1 output high timer1 output initial value 0: t0out polarity equal to tout logic input signal 1: t0out polarity reverse to tout logic input signal t0out polarity selection (tout logic or toutb) 0: bit(toutb) output through remout remout port output selection 0: remout output low 1: remout output high remout port bit control r/w r/w touts toutb 00: and of t0 output and t1 output 01: nand of t0 output and t1 output 10: or of t0 output and t1 output 11: nor of t0 output and t1 output t0init t1init 1: tout logic output through remout 0: timer0 output low 1: timer0 output high timer0 output initial value
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 41 figure 13-2 block diagram of timer0 btcl 76543210 t0cn t0ifs initial value: 00 h address: 0d0 h tm0 t0sl2 t0sl1 t0sl0 r/w r/w r/w r/w r/w r/w t0mod timer 0 mode register timer0 input clock select (fex=4mhz) 0: modulo-n 1: single mode 0: interrupt every count overflow 1: interrupt every 2nd count overflow timer0 single/moudol-n select timer0 interrupt select 0: count pause 1: count continuation timer0 counter continuation/pause control 0: timer/counter 1: input capture (ps1:not supporting timer0 interrupt select 0: timer0 stop 1: tiemr0 start after clear timer0 start/stop control r/w r/w cap0 t0st input cature) 000: ps0 250ns 001: ps1 500ns 010: ps2 1us 011: ps3 2us 100: ps4 4us 101: ps5 8us 110: ps11 512us 111: ec t0sl[2:0] mux 000 001 010 ps4 ps5 ps11 011 100 101 110 111 edge detector ec pin ifint2 int2 interrupt 01 10 11 capture ieds[5:4] comparator int2/r12 pin clear prescaler t0hc t0lc t0 counter (16-bit) [0d5 h ][0d6 h ] 16 bits msb lsb ps3 ps2 ps1 ps0 t0mod t0cn t0st delay 1 0 clear cap0 mux(16-bit) t0hmd t0hld t0lmd t0lld [0d3 h ][0d4 h ] [0d5 h ][0d6 h ] 1 0 cap0 output gen. interrupt gen. t0init t0out t0ifs ift0
HMS81004E/08e/16e/24e/32e 42 june 2001 ver 1.00 figure 13-3 block diagram of timer1 t1sl[2:0] mux 000 001 010 ps7 ps8 ps9 011 100 101 110 111 comparator clear prescaler t1 counter (8-bit) ps3 ps2 ps1 ps0 t1mod t1cn t1st [0d8 h ] output gen. interrupt gen. t1init t1out t1ifs ift1 ps10 t1 count reg. mux(8-bit) t1hd(8-bit) t1ld(8-bit) 10 [0d7 h ][0d8 h ] btcl 76543210 t1cn - initial value: 00 h address: 0d1 h tm1 t1sl2 t1sl1 t1sl0 r/w r/w r/w r/w r/w t1mod timer 1 mode register timer1 input clock select (fex=4mhz) 0: modulo-n 1: single mode 0: interrupt every count overflow 1: interrupt every 2nd count overflow timer1 single/moudol-n select timer1 interrupt select 0: count pause 1: count continuation timer1 counter continuation/pause control 0: timer1 stop 1: tiemr1 start after clear timer1 start/stop control r/w r/w t1st 000: ps0 250ns 001: ps1 500ns 010: ps2 1us 011: ps3 2us 100: ps7 32us 101: ps8 64us 110: ps9 128us 111: ps10 256us t1ifs
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 43 figure 13-4 block diagram of timer2 t2sl[2:0] mux 000 001 010 ps9 ps10 ps11 011 100 101 110 111 comparator clear prescaler t2 counter (8-bit) ps8 ps7 ps6 ps5 t2cn t2st [0d9 h ] output gen. interrupt gen. t2out ift2 ps12 t2 count reg. [0d9 h ] t2dr btcl 76543210 t2cn initial value: 00 h address: 0d2 h tm2 t2sl2 t2sl1 t2sl0 r/w r/w r/w r/w r/w timer 2 mode register timer2 input clock select (fex=4mhz) 0: count pause 1: count continuation timer2 counter continuation/pause control 0: timer2 stop 1: tiemr2 start after clear timer2 start/stop control t2st 000: ps5 8us 001: ps6 16us 010: ps7 32us 011: ps8 64us 100: ps9 128us 101: ps10 256us 110: ps11 512us 111: ps12 1,024us - - -
HMS81004E/08e/16e/24e/32e 44 june 2001 ver 1.00 2) timer0, timer1 timer0 and timer1 have an up-counter. when value of the up-counter reaches the content of timer data register (tdr), the up-counter is cleared to 00h, and interrupt (ift0, ift1) is occured at the next clock. for timer0, the internal clock (ps) and the external clock (ec ) can be selected as counter clock. but timer1 and timer2 use only internal clock. as internal clock. timer0 can be used as internal-timer which period is determined by timer data register (tdr). chosen as external clock, timer0 executes as event-counter. the counter ex- ecution of timer0 and timer1 is controlled by t0cn, t0st, cap0, t1cn, t1st, of timer mode register tm0 and tm1. t0cn, t1cn are used to stop and start timer0 and timer1 without clearing the counter. t0st, t1st is used to clear the counter. for clearing and starting the counter, t0st or t1st should be temporarily set to 0 and then set to 1. t0cn, t1cn, t0st and t1st should be set 1, when timer counting-up. controlling of cap0 enables timer0 as input capture. by programming of cap0 to 1, the period of signal from int2 can be measured and then, event counter value for int2 can be read. during counting-up, value of counter can be read- timer execution is stopped by the reset signal(re- set=l) note: in the process of reading 16-bit timer data, first read the upper 8-bit data. then read the lower 8-bit data, and read the upper 8-bit data again. if the earlier read up- per 8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct. if not, caution should be taken in the selection of upper 8-bit data. (example) 1) upper 8-bit read 0a 0a 2) lower 8-bit read ff 01 3) upper 8-bit read 0b 0b ===================== 0aff 0b01 figure 13-5 operation of timer0 ~ ~ timer 0 (ift0) interrupt t0 data time occur interrupt occur interrupt occur interrupt interrupt period up-count ~ ~ ~ ~ 0 1 2 3 4 5 6 match (tdr = t0) 0 register value t0 value
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 45 figure 13-6 start/stop operation of timer0 timer 0 (ift0) interrupt tdr time occur interrupt occur interrupt stop clear & start disable enable start & stop t0st t0cn control count up-count ~ ~ ~ ~ t0st = 0 t0st = 1 t0cn = 0 t0cn = 1 figure 13-7 input capture operation of timer0 t3 int2 t2 t1 t0
HMS81004E/08e/16e/24e/32e 46 june 2001 ver 1.00 3) single/modulo-n mode timer0 (timer1) can select initial (t0init, t1init of tm01) output level of timer output port. if initial level is l, low-data register value of timer data register is transferred to comparator and t0out (t1out) is to be low, if initial level is high? high -data register is transferred and to be high. single mode can be set by mode select bit (t0mod, t1mod) of timer mode reg- ister (tm0, tm1) to 1 when used as single mode, tim- er counts up and compares with value of data register. if the result is same, time out interrupt occurs and level of timer output port toggle, then counter stops as reset state. when used as modulo-n mode, t0mod (t1mod) should be set 0. counter counts up until the value of data register and occurs time-out interrupt. the level of timer output port toggle and repeats process of counting the value which is selected in data register. during modulo-n mode, if interrupt select bit (t0ifs, t1ifs) of mode register is 0, interrupt occurs on every time-out. if it is 1, interrupt occurs every second time- out. note: timer output is toggled whenever time out happen (4) timer 2 timer2 operates as a up-counter. the content of t2dr are compared with the contents of up-counter. if a match is found. timer2 interrupt (ift2) is generated and the up- counter is cleared to 00h. therefore, timer2 executes as a interval timer. interrupt period is determined by the count source clock for the timer2 and content of t2dr. when t2st is set to 1, count value of timer 2 is cleared and starts counting-up. for clearing and starting the timer2. t2st have to set to 1 after set to 0. in order to write a value directly into the t2dr, t2st should be set to 0. count value of timer2 can be read at any time. figure 13-8 operation diagram for single/modulo-n mode [ single mode ] [ module-n mode ] 8bit/16bit timer enable initial 8bit/16bit counting value toggle counting timer enable initial value toggle timer-output toggle int occurs (ifs=1) each 2nd time out int occurs (ifs=0) when time out
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 47 14. interrupts the HMS81004E/08e/16e/24e/32e interrupt circuits consist of interrupt mode register (mod), interrupt en- able register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit and master enable flag ("i" flag of psw). 8 interrupt sources are provided. the config- uration of interrupt circuit is shown in figure 14-1 . the HMS81004E/08e/16e/24e/32e contains 8 interrupt sources; 3 externals and 5 internals. nested interrupt ser- vices with priority control is also possible. software inter- rupt is non-maskable interrupt, the others are all maskable interrupts. - 8 interrupt source (2ext, 3timer, bit, wdt and key scan) - 8 interrupt vector - nested interrupt control is possible - programmable interrupt mode (hardware and software interrupt accept mode) - read and write of interrupt request flag are possible. - in interrupt accept, request flag is automatically cleared. figure 14-1 block diagram of interrupt int1 int2 watch dog timer wdtr ienl interrupt enable interrupt enable irql irqh interrupt vector address generator internal bus line register (higher byte) internal bus line register (lower byte) release stop to cpu interrupt master enable flag i-flag ienh priority control i-flag is in psw, it is cleared by di, set by ei instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by reti instruction, i-flag is set to 1 by hardware. int2r t0r bitr kscnr key scan basic interval timer int1r t2r t1r timer 2 timer 1 timer 0
HMS81004E/08e/16e/24e/32e 48 june 2001 ver 1.00 14.1 interrupt priority and sources each interrupt vector is independent and has its own pri- ority. software interrupt (brk) is also available. interrupt source classification is shown in table 14-1. 14.2 interrupt control register i flag of psw is a interrupt mask enable flag. when i flag = 0, all interrupts become disable. when i flag = 1, in- terrupts can be selectively enabled and disabled by con- tents of corresponding interrupt enable register. when interrupt is occured, interrupt request flag is set, and inter- rupt request is detected at the edge of interrupt signal. the accepted interrupt request flag is automatically cleared during interrupt cycle process. the interrupt request flag maintains 1 until the interrupt is accepted or is cleared in program. in reset state, interrupt request flag register (irqh, irql) is cleared to 0. it is possible to read the state of interrupt register and to mainpulate the contents of register and to generate interrupt. (refer to software inter- rupt) reset/interrupt symbol priority hardware reset reset - key scan kscnr 1 external interrupt1 int1r 2 external interrupt2 int2r 3 timer0 t0r 4 timer1 t1r 5 timer2 t2r 6 watch dog timer wdtr 7 basic interval timer bitr 8 brk instruction brk - table 14-1 interrupt source
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 49 14.3 interrupt accept mode the interrupt priority order is determined by bit (im1, im0) of imod register. the condition allow for accepting interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be 1. in reset state, these ip3 - ip0 registers become all 0. . figure 14-2 interrupt enable & request flag 0: disable 1: enable value r/w initial value: 000- 000- b address: 0ce h ienh int1e msb lsb t0e t1e int2e r/w external interrupt 1 initial value: -00- ---- b address: 0cc h ienl msb lsb timer1 r/w r/w r/w r/w basic interval timer watchdog timer external interrupt 2 key scan wdte r/w r/w --- -- bite - -- kscne t2e timer2 timer0 r/w initial value: 000- 000- b address: 0cf h irqh int1r msb lsb t0r t1r int2r r/w external interrupt 1 initial value: -00- ---- b address: 0cd h irql msb lsb timer1 r/w r/w r/w r/w basic interval timer watchdog timer external interrupt 2 key scan wdtr r/w r/w --- -- bitr - -- kscnr t2r timer2 timer0
HMS81004E/08e/16e/24e/32e 50 june 2001 ver 1.00 14.4 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an instruction. inter- rupt acceptance sequence requires 8 f xin after the completion of the current instruction execution. the interrupt service task is ter- minated upon execution of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to 0 to temporarily disable the acceptance of any follow- ing maskable interrupts. when a non-maskable inter- rupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. l figure 14-3 interrupt accept mode & selection by ip3~ip0 btcl 76543210 im 1 initial value: --00_0000 b address: 0ca h imod ip1 ip0 r/w r/w r/w r/w r/w r/w im0 interrupt mode register selection interrupt 00: fixed by hardware 01: changeable by ip3~ip0 priority r/w r/w -- 0001: kscnr 0010: int1r 0011: int2r 0101: t0r 0110: t1r 0111: t2r 1010: wdtr 1011: bitr ip 2 ip 3 1x: interrupt is inhibited
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 51 figure 14-4 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i-flag should be set to 1 by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these regis- ters are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general-purpose registers. example: register save using push and pop instructions general-purpose register save/restore using push and pop instruc- tions; v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. external interrupt1 012 h 0e3 h 0fff8 h 0fff9 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for exteranl interrupt1 and the entry address of the interrupt service program. vector table address intxx: push a push x push y ;save acc. ;save x reg. ;save y reg. interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return
HMS81004E/08e/16e/24e/32e 52 june 2001 ver 1.00 14.5 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk inter- rupt is generated, b-flag of psw is set to distinguish brk from tcall 0. each processing step is determined by b-flag as shown in figure 14-5 figure 14-5 execution of brk/tcall0 14.6 multi interrupt if two requests of different priority levels are received simulta- neously, the request of higher priority level is serviced. if re- quests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hard- ware which request is serviced. however, multiple processing through software for special fea- tures is possible. generally when an interrupt is accepted, the i- flag is cleared to disable any further interrupt. but as user sets i- flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. example: during timer1 interrupt is in progress, int1 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#40h ; enable int1 only ldm ienl,#00h ; disable other ei ; enable interrupt : : : : ldm ienh,#0ffh ; enable all interrupts ldm ienl,#0ffh pop y pop x pop a reti figure 14-6 execution of multi interrupt 14.7 external interrupt the external interrupt on int1 and int2 pins are edge triggered depending on the edge selection register ieds (address 0d8 h ) as shown in figure14-7. b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1 enable int1 timer 1 service int1 service main program service occur timer1 interrupt occur int1 ei disable other enable int1 enable other in this example, the int1 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable ei in the timer1 routine.
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 53 response time the int1 ~ int2 edge are latched into ifint1 ~ ifint2 at every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be ex- ecuted. the div itself takes twelve cycles. thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. figure 14-8 shows interrupt response timings. figure 14-8 interrupt response timing diagram 14.8 key scan input processing key scan interrupt is generated by detecting low or high input from each input pin (r0, r1) is one of the sources which release standby (sleep, stop) mode. key scan ports are all 16bit which are controlled by standby mode release register (smrr0, smrr1). key input is consid- ered as interrupt, therefore, kscne bit of iehn should be set for correct interrupt executing, sleep mode and stop mode, the rest of executing is the same as that of external interrupt. each smrr register bit is allowed for each port (for bit= 0, no key input, for bit= 1, key input avail- able). at reset, smrr becomes 00h. so, there is no key input source. figure 14-7 external interrupt block diagram ifint1 int1 pin int1 interrupt ifint2 int2 pin int2 interrupt ieds [0cbh] edge selection register 2 2 btcl 76543210 ied2h initial value: 0000_0000 b address: 0cb h ieds - w ext. int. edge selection reg. 01: falling edge selection 10: rising edge selection ied2* -- 11: both edsg selection - www ied2l ied1h ied1l 01: falling edge selection 10: rising edge selection ied1* 11: both edsg selection interrupt goes active interrupt latched interrupt processing interrupt routine 8 f xin period max. 12 f xin period
HMS81004E/08e/16e/24e/32e 54 june 2001 ver 1.00 standby release level control register (srlc) can select the key scan input level l or h for standby release by each bit pin (r0, r1). standby release level control register (srlc) is write-only register and initialized as 00h in re- set state. figure 14-9 block diagram of key scan block btcl 76543210 initial value: 00 h address: 0dc h smrr0 w kr07 r03 r02 r01 r04 r05 r06 r07 r00 r0 port logic r13 r12 r11 r14 r15 r16 r17 r10 smrr0 srlc0 r1 port logic smrr1 srlc1 internal key scan input w w w w w w w kr06 kr05 kr04 kr03 kr02 kr01 kr00 kr0* 1: select 0: no select btcl 76543210 initial value: 00 h address: 0dd h smrr1 w kr17 w w w w w w w kr16 kr15 kr14 kr13 kr12 kr11 kr10 kr1* 1: select 0: no select btcl 76543210 initial value: 00 h address: 0f6 h srlc0 w klr07 w w w w w w w klr06 klr05 klr04 klr03 klr02 klr01 klr00 klr0* 1: high 0: low btcl 76543210 initial value: 00 h address: 0f7 h srlc1 w klr17 w w w w w w w klr16 klr15 klr14 klr13 klr12 klr11 klr10 klr1* 1: high 0: low
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 55 15. standby function 15.1 sleep mode sleep mode can be entered by setting the bit of sleep mode register (slpm). in the mode, cpu clock stops but oscillator keeps running. b.i.t and a part of peripheral hardware execute, but prescalers output which provide clock to peripherals can be stopped by program. (except, ps10 cant stopped.) in sleep mode, more consuming power can be saved by not using other peripheral hardware except for b.i.t. by setting enpck (peripheral clock con- trol bit) of ckctlr (clock control register) to 0, periph- eral hardware halted, and sleep mode is entered. to release sleep mode by bitr (basic interval timer inter- rupt), bit10 of prescaler should be selected as b.i.t input clock before entering sleep mode. nop instruction should be follows setting of sleep mode for rising pre- charge time of data bus line. (ex) setting of sleep mode : set the bit of sleep ; mode register (slpm) nop : nop instruction 15.2 stop mode stop mode can be entered by stop instruction during program. in stop mode, oscillator is stopped to make all clocks stop, which leads to less power consumption. all registers and ram data are preserved. nop instruction should be follows stop instruction for rising precharge time of data bus line. (ex) stop : stop instruction execution nop : nop instruction sleep mode control register (w) slpm address : 0f0 h initial value : -------0b - slpm0 1: sleep mode clock control register (w) ckctlr address : 0c7 h initial value : --110111b 0 1 2 3 4 5 6 7 enpck 0: stopped 1: provided ---- -- 0: sleep mode release 0
HMS81004E/08e/16e/24e/32e 56 june 2001 ver 1.00 15.3 standby mode release release of standby mode is executed by reset input and interrupt signal. register value is defined when reset. when there is a release signal of stop mode (interrupt, reset input), the instruction execution starts after stabi- lization oscillation time is set by value of bts2 ~ bts0 and set enpck to 1. figure 15-1 block diagram of standby circuit osc circuit clock pulse generator cpu clock release signal from interrupt resetb stop s r q s r q control signal overflow detection bit7 prescaler clear mux basic interval timer clear release signal sleep stop resetb o o kscn(key input) o o int1,int2 o o b.i.t. o table 15-1 release signal of standby mode
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 57 release factor release method resetb by resetb pin=low level, standby mode is releas and system is initialized kscn(key input) standby mode is released by low input of selected pin by key scan input(smrr0,smrr1). in case of interrupt mask enable flag= 0, program executes just after standby instruction, if flag= 1 enters each interrupt service routine. int1,int2 when external interrupt (int1,int2) enable flag is 1, standby mode is released at the rising edge of each terminal. when standby mode is released at interrupt. mask enable flag= 0, program executes from the next instruction of standby instruction. when 1, enters each interrupt service routine. basic interval timer(ifbit) when b.i.t. is executed only by bit10 of prescaler(ps10), sleep mode can be released. interrupt release sleep mode , when bit interrupt enable flag is 1. when standby mode is released at interrupt. mask enable flag= 0, program executes from the next instruction of sleep instruction. when 1, enters each interrupt service routine. table 15-2 figure 15-2 block diagram of standby circuit [sleep mode] xin sleep command sleep mode release by interrupt reset longer than 2 machine cycle [stop mode] xin stop mode release by interrupt reset stable osc.time program setting time by ckctlr longer than stabe osc. time
HMS81004E/08e/16e/24e/32e 58 june 2001 ver 1.00 15.4 release operation of standby mode after standby mode is released, the operation begins ac- cording to content of related interrupt register just before standby mode start (figure 15-3). (1) interrupt enable flag(i) of psw = 0 release by only interrupt which interrupt enable flag = 1, and starts to execute from next to standby instruction (sleep or stop). (2) interrupt enable flag(i) of psw = 1 released by only interrupt which each interrupt enable flag = 1, and jump to the relevant interrupt service routine. note: when stop instruction is used, b.i.t should guar- antee the stabilization oscillation time. thus, just before en- tering stop mode, clock of bit10 (ps10) of prescaler is selected or peripheral hardware clock control bit (enpck) to 1, therefore the clock necessary for stabilization oscil- lation time should be input into b.i.t. otherwise, standby mode is released by reset signal. in case of interrupt re- quest flag and interrupt enable flag are both 1, standby mode is not entered. . figure 15-3 standby mode release flow stop command interrupt request gen. int. enable reg. 0 1 standby mode psw i flag standby mode release interrupt service routine standby next command execution 0 1
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 59 internal circuit sleep mode stop mode oscillator active stop internal cpu stop stop register retained retained ram retained retained i/o port retained retained prescaler active retained basic interval timer ps10 selected:active others: stop stop watch-dog timer stop stop timer stop stop address bus,data bus retained retained table 15-3 operation state in standby mode
HMS81004E/08e/16e/24e/32e 60 june 2001 ver 1.00 16. reset function 16.1 external reset the reset pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uf capacitor for stable system initialization. the reset pin contains a schmitt trigger with an internal pull-up resistor. 16.2 power on reset power on reset circuit automatically detects the rise of power voltage (the rising time should be within 50ms) the power voltage reaches a certain level, reset terminal is maintained at l level until a crystal ceramic oscillator oscillates stably. after power applies and starting of oscil- lation, this reset state is maintained for about oscillation cycle of 219 (about 65.5ms : at 4mhz).the execution of built-in power on reset circuit is as follows : (1) latch the pulse from power on detection pulse gener- ator circuit, and reset prescaler, b.i.t and b.i.t overflow detection circuit. (2) once b.i.t overflow detection circuit is reset. then, prescaler starts to count. (3) prescaler output is inputted into b.i.t and ps10 of prescaler output is automatically selected. if overflow of b.i.t is detected, overflow detection circuit is set. 4) reset circuit generates maximum period of reset pulse from prescaler and b.i.t figure 16-1 reset pin connection reset gnd 0.1uf capacitor
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 61 note: when power on reset, oscillator stabilization time doesn`t include osc. start time. figure 16-2 block diagram of power on reset circuit reset gnd 0.1uf gnd vdd internal reset power on detect pulse generator osc circuit prescaler basic interval timer b.i.t. overflow detction circuit clear clear clear ps10 msb figure 16-3 oscillator stabiliaztion diagram vdd osc. start time prescaler count start
HMS81004E/08e/16e/24e/32e 62 june 2001 ver 1.00 16.3 low voltage detection mode (1) low voltage detection condition an on board voltage comparator checks that vdd is at the required level to ensure correct operation of the device. if vdd is below a certain level, low voltage detector forces the device into low voltage detection mode. (2) low voltage detection mode there is no power consumption except stop current, stop mode release function is disabled. all i/o port is config- ured as input mode and data memory is retained until volt- age through external capacitor is worn out. in this mode, all port can be selected with pull-up resistor by mask op- tion. if there is no information on the mask option sheet ,the default pull up option (all port connect to pull-up resis- tor ) is selected. (3) release of low voltage detection mode reset signal result from new battery(normally 3v) wakes the low voltage detection mode and come into normal reset state. it depends on user whether to execute ram clear routine or not figure 16-4 timing diagram of reset main program oscillator (x in pin) ? ? fffe ffff stabilization time reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ adl and adh are start addresses of interrupt service routine as vector contents. figure 16-5 low voltage vs temperature 1.55 1.60 1.65 1.70 1.75 1.80 1.85 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 lvd(v) temperature ( c)
HMS81004E/08e/16e/24e/32e june 2001 ver 1.00 63 (4) sram back-up after low voltage detection. figure 16-6 oscillator stabiliaztion diagram interrupt disable stop release disable all i/o port input mode remout port low level osc stop all i/o port pull-up on mask option sram data retention until vret table 16-1 the operation after low voltage detection vdd 2v(min.) 1.7v(typ.20 c ) 0.7v(vret) 0v 3v about hours depend on vdd-gnd capacitor sram data backup user removes batteries user replaces batteries time low voltage detetion point power on reset (sram retention) power on reset (sram unstable)
HMS81004E/08e/16e/24e/32e 64 june 2001 ver 1.00 (5) s/w flow chart example after reset using sram back-up figure 16-7 s/w flow chart example after reset using sram back-up reset check the sram value stack pointer initialize sram data valid? use saved sram value clear all ram area n y (ram pattern, checksum) main routine
appendix
a. mask order sheet 1. customer information company name 2. device information 4. marking specification 5. delivery schedule customer sample date yyyy mm dd risk order yyyy mm dd quantity hynix confirmation application order date te l : fax: package 20sop 20pdip 6. rom code verification verification date: yyyy mm dd approval date: yyyy mm dd please confirm our verification data. i agree with your verification data and confirm you to m ake m ask set. check sum: te l : f a x : name & signature: te l : fax: name & signature: mask data file name: ( .otp) (please check mark into ) pcs pcs check sum ( @27c256) customer should write inside thick line box. this box is written after 6.verification. 28sop 28skdip 24sop 24skdip yyww korea customers logo customer logo is not required. yyww korea hms810 customers part number if the customer logo must be used in the special mark, please submit a clean original of the logo. 04/08/16/24/32 name&signature: june 2001 mask order & verification sheet hms810 e -ue e -ue lot number hynix rom code number yyyy mm dd 28pin die hms810 e -ue 3. inclusion of pull-up resistor in low volatage detection mode port r00 r01 r02 r03 r04 r05 r06 r07 r10 r11 r12 r13 r14 r15 r16 r17 r20 r21 r22 r23 r24 y/n *2 *2 *2 *2 *1 *1 *1 *1 *1 : is not avilable for 20pin. so default option is pull-up on. *2 : is not avilable for 20pin & 24pin. so default option is pull-up on.
appendix june 2001 ver 1.00 lxxi b. instruction b.1 terminology list terminology description a accumulator x x - register y y - register psw program status word #imm 8-bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto-increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000 h ~0fff h ) rel relative addressing data upage u-page (0ff00 h ~0ffff h ) offset address n table call number (0~15) + addition x upper nibble expression in opcode y upper nibble expression in opcode - subtraction multiplication / division ( ) contents expression and or ? exclusive or ~not ? assignment / transfer / shift left ? shift right ? exchange = equal 1 not equal 0 bit position 1 bit position
appendix lxxii june 2001 ver 1.00 b.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
appendix june 2001 ver 1.00 lxxiii b.3 instruction set arithmetic / logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ? ( a ) + ( m ) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ? ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents ( a ) - ( m ) 22 cmp dp 45 2 3 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : ( dp ) ? ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----z- 39 dec dp a9 2 4 m ? ( m ) - 1 n-----z- 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 n-----z- 42 dec x af 1 2 n-----z- 43 dec y be 1 2 n-----z- ? ? ? ? ? ? ? ? 76543210 ? 0 ? c
appendix lxxiv june 2001 ver 1.00 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ? ( a ) ? ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----zc 54 inc dp 89 2 4 m ? ( m ) + 1 n-----z- 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 n-----z- 57 inc x 8f 1 2 n-----z- 58 inc y 9e 1 2 n-----z- 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ? ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry 81 sbc dp 25 2 3 a ? ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero, ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- no. mnemonic op code byte no cycle no operation flag nvgbhizc ? ? ? ? ? ? ? ? 76543210 0 ? ? c ? ? ? ? ? ? ? ? 76543210 c ? ? ? ? ? ? ? ? 76543210 c
appendix june 2001 ver 1.00 lxxv register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ? ( m ) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8 lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ? ( m ) , x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) ? imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ? ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ? ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) ? a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) ? x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) ? y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a ? x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp ? x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a ? y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y --------
appendix lxxvi june 2001 ver 1.00 16-bit operation bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ? ( ya ) ( dp +1 ) ( dp ) nv--h-zc 2cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) - (dp+1)(dp) n-----zc 3decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ? ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ? ( dp+1) ( dp ) + 1 n-----z- 5 ldya dp 7d 2 5 load ya ya ? ( dp +1 ) ( dp ) n-----z- 6 stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ? ya -------- 7 subw dp 3d 2 5 16-bits subtract without carry ya ? ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ? ( a ) ( m ) , n ? ( m 7 ) , v ? ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ? 0 -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -------- 7 clrc 20 1 2 clear c-flag : c ? 0 -------0 8 clrg 40 1 2 clear g-flag : g ? 0 --0----- 9 clrv 80 1 2 clear v-flag : v ? 0 -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? ( c ) ? ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? ( c ) ? ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ? ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ? ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ? ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? ( c ) ~( m .bit ) -------c 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ? 1 -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ? 1 -------- 19 setc a0 1 2 set c-flag : c ? 1 -------1 20 setg c0 1 2 set g-flag : g ? 1 --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) ? c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ? ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ? ( m ) ( a ) n-----z-
appendix june 2001 ver 1.00 lxxvii branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ? ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ? ( pc ) + rel 5 bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ? ( pc ) + rel -------- 6 bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ? ( pc ) + rel -------- 7 beq rel f0 2 2/4 branch if equal if ( z ) = 1 , then pc ? ( pc ) + rel -------- 8 bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ? ( pc ) + rel -------- 9 bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ? ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if plus if ( n ) = 0 , then pc ? ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ? ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ? ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ? ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ? ( pc h ), sp ? sp - 1, m(sp) ? (pc l ), sp ? sp - 1, if !abs, pc ? abs ; if [dp], pc l ? ( dp ), pc h ? ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) 1 ( m ) , then pc ? ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 1 0 , then pc ? ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc ? jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ), sp ? sp - 1, pc l ? ( upage ), pc h ? 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ),sp ? sp - 1, pc l ? (table vector l), pc h ? (table vector h) --------
appendix lxxviii june 2001 ver 1.00 control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt : b ? 1, m(sp) ? (pc h ), sp ? sp-1, m(s) ? (pc l ), sp ? sp - 1, m(sp) ? (psw), sp ? sp -1, pc l ? ( 0ffde h ) , pc h ? ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable all interrupts : i ? 0 -----0-- 3 ei e0 1 3 enable all interrupt : i ? 1 -----1-- 4 nop ff 1 2 no operation -------- 5 pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) 6 pop x 2d 1 4 sp ? sp + 1, x ? m( sp ) -------- 7 pop y 4d 1 4 sp ? sp + 1, y ? m( sp ) 8 pop psw 6d 1 4 sp ? sp + 1, psw ? m( sp ) restored 9 push a 0e 1 4 m( sp ) ? a , sp ? sp - 1 10 push x 2e 1 4 m( sp ) ? x , sp ? sp - 1 -------- 11 push y 4e 1 4 m( sp ) ? y , sp ? sp - 1 12 push psw 6e 1 4 m( sp ) ? psw , sp ? sp - 1 13 ret 6f 1 5 return from subroutine sp ? sp +1, pc l ? m( sp ), sp ? sp +1, pc h ? m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp ? sp +1, psw ? m( sp ), sp ? sp + 1, pc l ? m( sp ), sp ? sp + 1, pc h ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------

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